`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/21 16:29:07
// Design Name: 
// Module Name: in
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module in();
    reg up;
    reg down;
    reg left;
    reg right;
    reg set;
    reg sec;
    reg [5:0]s;
    reg [5:0]m;
    reg [4:0]h;
    timer t1(sec,set,up,down,left,right,s,m,h);
    always begin
        sec=1;
        #2 sec=0;
        #2;
    end
    initial begin
        sec = 0;
        set = 0;
        #16;
        set = 1;
        #10;
        up = 1;
        #10;
        up = 0;
        #10;
        down = 1;
        #10;
        down = 0;
        #16;
        set = 0;
    end
endmodule
